1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a transfer gate which uses an insulated gate electric field effect transistor (referred to as a MOS transistor, hereinafter).
2. Description of the Related Art
FIG. 1 is a circuit diagram showing one constitutional example of a conventional semiconductor device.
Referring to FIG. 1, this conventional semiconductor device is composed of an analog switch 130, which is for transmitting an analog signal from an input pad to an output pad, and a protective circuit 20, which is for protecting the analog switch 130. A signal input from an analog signal 9 is transmitted through the analog switch 130 and the protective circuit 20 to a bonding pad 1, a signal input from the bonding pad 1 is transmitted through the protective circuit 20 and the analog switch 130 to the analog signal 9, and so on. In the analog switch 130, there are provided side by side a P type transfer gate 4 and an N type transfer gate 5, to whose gate terminals reverse phase control signals 10 are input by inverters 6a and 6b respectively. In the protective circuit 20, there are provided a P type protective transistor 2, with its source and gate terminals connected to a power supply potential 7 and its drain terminal connected to the bonding pad 1, and an N type protective transistor 3, with its source and gate terminals connected to a ground potential and its drain terminal connected to the bonding pad 1.
FIG. 2 is a view showing a layout example of the analog switch 130 shown in FIG. 1.
FIG. 3(a) is a section view taken along the line C-C' of the analog switch 130 shown in FIG. 2, and FIG. 3(b) is a section view taken along the line D-D' of the analog switch 130 shown in FIG. 2.
Referring to FIG. 2, the bonding pad 1 is connected through a second layer metallic wiring 101-1 and first layer metallic wirings 102-1 and 102-4 to the N type diffusion layers 104-1 and 104-3 of the N type transfer gate 5 and to the P type diffusion layers 103-2 and 103-4 of the P type transfer gate 4. Thereby, the bonding pad 1 and the analog switch 130 are interconnected.
Herein, an N type diffusion layer 104-2 in the internal side of the N type transfer gate 5 and a P type diffusion layer 103-3 in the internal side of the P type transfer gate 4 are connected through a first layer metallic wiring 102-7 to an internal circuit.
Furthermore, in order to prevent latching up, the N type transfer gate 5 is surrounded by a P type diffusion layer 103-1, which is connected to a ground potential (Vss) 8. Also, the P type transfer gate 4 is surrounded by an N type diffusion layer 104-4, which is connected to the power supply potential (Vdd) 7.
The operation of the analog switch thus constructed will be described below.
When a control signal 10 is at a low level, the P type transfer gate 4 and the N type transfer gate 5 are both made to be non-conductive, and thus the outside and the inside of the chip are electrically shielded from each other.
When a control signal 10 is at a high level, the P type transfer gate 4 and the N type transfer gate 5 are both made to be conductive, and thus a signal having an optional potential between the ground potential 8 and the power supply potential 7 is transmitted from the external bonding pad 1 to the internal analog signal 9, or from the internal analog signal 9 to the external bonding pad 1.
Next, the operation of the protective circuit 20 for preventing the breakdown of the transistor, which constitutes the analog switch 130, will be described. This breakdown occurs when an excessive voltage of static electricity and so on is applied from the outside.
When a positive excessive voltage is applied to the ground from the outside, first a breakdown occurs in the N type diffusion layer in the gate terminal side of the drain terminal of the N type protective transistor 3 and thus a current is made to flow to a P type well. A breakdown voltage in this case will be referred to as BVDS.
Then, by lowering of the voltage caused by the current which has flown into the P type well, the N type diffusion layer of the source terminal and a diode is formed by the P type well are forward biased, a parasitic NPN type bipolar transistor is formed by the drain terminal, the P type well and the source terminal is made to be in an operation state (referred to as a snapback operation state, hereinafter), and an excessive current coming from the outside is made to flow to the ground.
After the snapback operation state has been realized, a potential for the drain terminal of the N type protective transistor 3 is fixed at a value lower than that of the breakdown voltage of the N type diffusion layer, which has been connected to the bonding pad 1 of the N type transfer gate 5, and thereby the analog switch 130 is prevented from being broken down.
When a negative excessive voltage is applied to the ground from the outside, the drain diffusion layers of the N type protective transistor 3 are forward biased, a current is made to flow to the ground through the P type well, and thereby the analog switch 130 is prevented from being broken down.
When a positive excessive voltage is applied to the power source from the outside, the drain diffusion layers of the P type protective transistor 2 are forward biased, a current is made to flow to the power source through an N type well, and thereby the analog switch 130 is prevented from being broken down.
Also, when a negative excessive voltage is applied to the power source from the outside, first a breakdown occurs in the P type diffusion layer in the gate terminal side of the drain terminal of the P type protective transistor 2, and thus a current is made to flow to the N type well.
Then, by lowering of the voltage caused by the current which has flown into the N type well, the P type diffusion layer of the source terminal and a diode is formed by the N type well are forward biased, a parasitic PNP type bipolar transistor is formed by the drain terminal, the N type well and the source terminal are made to be in a snapback operatation state and thus an excessive current coming from the outside is made to flow to the power source.
After the snapback operation state has been realized, a potential for the drain terminal of the P type protective transistor is fixed at a value lower than that of the breakdown voltage of the P type diffusion layer, which has been connected to the bonding pad 1 of the P type transfer gate 4, and thereby the analog switch is prevented from being broken down.
FIG. 4 is a circuit diagram showing another constitutional example of a conventional semiconductor device.
Referring to FIG. 4, the conventional semiconductor device of this example is composed of a NOR type output circuit 140, and a protective circuit 20, which is for protecting the NOR type output circuit 140. A signal input from a data signal 18 is transmitted through the NOR type output circuit 140 and the protective circuit 20 to a bonding pad 1, a signal input from the bonding pad 1 is transmitted through the protective circuit 20 and the NOR type output circuit 140 to the data signal 18, and so on. In the NOR type output circuit 140, there are provided a P type transistor 13 and an N type transistor 16, which are connected to a control signal 17, and P type transistor 14 and an N type transistor 15, which are connected to the data signal 18. In the protective circuit 20, there are provided a P type protective transistor 2 with its source and gate terminals connected to a power supply potential 7 and its drain terminal connected to the bonding pad 1, and an N type protective transistor 3 with its source and gate terminals connected to a ground potential and its drain terminal connected to the bonding pad 1.
FIG. 5 is a view showing the layout example of a NOR type outout circuit shown in FIG. 4.
Referring to FIG. 5, a P type diffusion layer 103-4 in the drain part of a vertically placed P type transistor is connected to the pad through a first layer metallic wiring 102-1, a contact C2 between first and second layer metallic wirings and a second layer metallic wiring 101-1.
As in the case of the semiconductor device shown in FIG. 2, because of corner parts formed in the diffusion layers, an excessive current flows to the corner parts in a concentrated manner when an excessive voltage is applied from the outside, and consequently the diffusion layers are destroyed.
The application of a positive excessive voltage to the ground, including the N type transfer gate 5, will be described in detail below.
The drain terminal of the N type protective transistor 3 and the N type diffusion layer of the N type transfer gate 5 are almost at the same potential, because these are interconnected by a low resistant metallic wiring.
For the N type diffusion layer of the N type transfer gate 5, a breakdown occurs in its field oxidized film end. A breakdown voltage in this case will be referred to as BVJ.
Herein, BVJ depends on the layout of the analog switch.
FIG. 6 is a view showing a breakdown voltage for the semiconductor device shown in FIG. 2.
Referring to FIG. 6, a BVJ 1 is a breakdown voltage when the diffusion layer end of a certain side does not intersect that of another side as in the case of the N type diffusion layer 104-2 shown in FIG. 2. A BVJ 2 is a breakdown voltage when the diffusion layer end of a certain side intersects that of another diffusion layer as in the case of the N type diffusion layers 104-1 and 104-3. A BVDS is a breakdown voltage for the N type protective transistor 3.
In the N type diffusion layers 104-1 and 104-3, a breakdown occurs in the corner parts of the diffusion layers before the diffusion layer edges, because electric fields concentrate therein. Consequently, the BVJ 2 is lower than the BVJ 1, which is a breakdown voltage when there are no corner parts in the diffusion layers.
As shown in FIG. 6, when the BVJ 2 for the N type diffusion layer of the N type transfer gate is lower than the BVDS for the N type protective transistor, if an excessive voltage is applied from the outside, a breakdown occurs in the corner part of the N type diffusion layer of the N type transfer gate before the N type protective transistor functions as a protective transistor, and since currents concentrate in the narrow corner part of the diffusion layer, the diffusion layer is destroyed.
The foregoing description was for the case when a positive excessive voltage was applied to the ground. It should be understood, however, that when a negative excessive voltage is applied to the power source, by replacing the N type diffusion layer of the N type transfer gate 5 and the N type protective transistor 3, described above, respectively with the P type diffusion layer of the P type transfer gate 4 and the P type protective transistor 2, the P type diffusion layer of the P type is destroyed by the excessive voltage.
As apparent from the foregoing, there was a problem inherent in the conventional semiconductor device. Specifically, when an excessive voltage was applied from the outside, there was a possibility of a breakdown in the device, caused by a voltage lower than a breakdown voltage in the protective transistor.